TSB951ILT datasheet(37/38 Pages) STMICROELECTRONICS

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Figure 50.

Maximum output current for safe operation on SO8 package ................................... 22

Figure 51.

Maximum output current for safe operation on DFN8 package .................................. 23

Figure 52.

Test configuration for RISO ........................................................... 23

Figure 53.

Inverting amplifier configuration with parasitic input capacitances ................................ 24

Figure 54.

Settling time measurement configuration ................................................. 25

Figure 55.

Low-side current sensing schematic .................................................... 26

Figure 56.

SOT23-5 package outline ........................................................... 28

Figure 57.

SO8 package outline ............................................................... 29

Figure 58.

DFN8 3x3 exposed pad, wettable flank package outline and mechanical data........................ 30

Figure 59.

DFN8 3x3 exposed pad, wettable flank footprint data......................................... 31

TSB951, TSB952

List of figures

DS14576 - Rev 3

page 37/38

TSB951ILT Datasheet(PDF) 37 Page - STMicroelectronics