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MB85AS8MT Datasheet(PDF) 13 Page - RAMXEED LIMITED

Part # MB85AS8MT
Description  8M (1024 K x 8) Bit SPI
PDF  30 Pages
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Manufacturer  RAMXEED [RAMXEED LIMITED]
Direct Link  https://www.ramxeed.com/
Logo RAMXEED - RAMXEED LIMITED

MB85AS8MT Datasheet(HTML) 13 Page - RAMXEED LIMITED

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MB85AS8MT
DS501-00060-2v2-E
13
2. WIP polling
After the last writing data was input, writing to the nonvolatile memory needs tWC waiting time from the rising
edge of CS. This tWC time becomes larger than a minimum clock cycle. Production variation and operating
condition are considered, and this maximum tWC value is defined. In the usual operation, this tWC time is
shorter than the maximum value. Therefore, MB85AS8MT supports WIP polling to improve memory access
by optimizing the waiting time.
After starting the data writing to nonvolatile memory, MB85AS8MT sets “1” to a volatile register related to
the WIP bit in status register. After finished the writing operation, reset this WIP bit from “1” to “0”. Although
the usual commands are not executable during this writing process, only the RDSR command is acceptable.
RDSR command outputs the value of status register to SO. It is possible to confirm if the internal writing
operation to nonvolatile memory is finished or not, by checking the corresponding bit to WIP in output data
from SO.
RDSR command also outputs the WPEN, BP1 and BP0 of status register to SO. In the polling after WRSR
command, MB85AS8MT outputs the WPEN, BP1 and BP0 data which is set before the writing to nonvolatile
memory is completed. On the other hand for WEL and WIP, MB85AS8MT outputs (WEL,WIP)=2'b11 when
the writing to nonvolatile memory is not completed. When it is competed, outputs (WEL,WIP)=2'b00.
If continuously sending clocks to SCK during CS = low, it is also possible to keep on outputting WPEN to
WIP bits in status register in unit of 8 cycles since 17th clock. In case the WIP polling is applied, WIP and
WEL bits in status register output to SO by RDSR command are updated regularly.
Figure shows the example of RDSR command input with continuously sending clocks over 17 during CS =
low, before the writing process of WRSR command is finished.
CS
SCK
SI
WPEN
XXX BP1 BP0 XX
SO
busy
wip
wel
WRSR
RDSR
WPEN
X
BP1
XX
BP0
WEL
WIP
WPEN
X
BP1
XX
BP0
WEL
WIP
(Write process situation)
(Internal volatile register for WIP)
(Internal volatile register for WEL)



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