STM32MP251D datasheet(40/234 Pages) STMICROELECTRONICS

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•

Independent clock: a choice of independent clock sources that allows the I2C communication speed to be

independent from the PCLK reprogramming

•

Wake-up from Stop mode on address match

•

Programmable analog and digital noise filters

•

1-byte buffer with DMA capability

3.50

Improved inter-integrated circuit (I3C1/2/3/4)

STM32MP25xA/D devices embed four I3C interfaces, that handle communication between the device and others

that are all connected on an I3C bus, like sensors and host processors.

The I3C peripheral implements all required features of the MIPI I3C specification v1.1. It can control all I3C

bus

‑specific sequencing, protocol, arbitration and timing, and can be acting as controller (formerly known as

master), or as target (formerly known as slave).

The I3C peripheral, acting as controller, improves the I2C interface features still preserving some backward

compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C fast

‑mode (Fm) or legacy I2C

fast

‑mode plus (Fm+), provided that this latter does not perform clock stretching.

The I3C peripheral can be used with DMA in order to off

‑load the CPU.

•

MIPI I3C specification v1.1 (see I3C section in the reference manual), as:

–

I3C primary controller

–

I3C secondary controller

–

I3C target

•

Registers configuration from the host application via the APB slave port

•

Queued transfers:

–

Transmit FIFO (TX

‑FIFO) for data bytes/words to be transmitted on I3C bus

–

Receive FIFO (RX

‑FIFO) for received data bytes/words on I3C bus

–

Control FIFO (C

‑FIFO) for control words to be sent on I3C bus, when controller

–

Status FIFO (S

‑FIFO) for status words as received on I3C bus, when controller

–

For each FIFO, optional DMA mode with a dedicated DMA channel

•

Messages:

–

Legacy I2C read/write messages to legacy I2C targets in Fm/Fm+

–

I3C SDR read/write private messages

–

I3C SDR (write) broadcast CCC messages

–

I3C SDR read/write direct CCC messages

•

Frame

‑level management, when controller:

–

Software

‑triggered or hardware‑triggered transfer

–

Optional C

‑FIFO and TX‑FIFO preload

–

Multiple messages encapsulation

–

Optional arbitrable header

•

Programmable bus timing, when controller

–

SCL high and low period

–

SDA hold time

–

Bus free (minimum) time (between a stop and a start)

–

Bus available/idle condition time, maximum clock stall time

–

Minimum clock stall time during 9th bit

•

Target

‑initiated requests management:

–

‑band interrupts, with programmable IBI payload (up to 4 bytes)

–

Bus control request, with recovery flow support and hand

‑off delay

–

Hot

‑join mechanism

–

Pending read notification

STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

Functional overview

DS14285 - Rev 2

page 40/234

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