STM32H563AI datasheet(21/270 Pages) STMICROELECTRONICS

21 / 270 page

DS14258 Rev 5

21/270

STM32H562xx and STM32H563xx

Functional overview

•

Supported cache accesses:

–

supports both write-back and write-through policies (selectable with AHB

bufferable attribute)

–

read and write-back always allocated

–

write-through always non-allocated (write-around)

–

supports byte, half-word and word writes

•

TrustZone security support

•

Maintenance operations for software management of cache coherency:

–

full cache invalidation (non interruptible)

–

address range clean and/or invalidate operations (background task, interruptible)

•

Error management: detection of error for master port request initiated by DCACHE (line

eviction or clean operation), with optional interrupt raising

3.3

Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory

and to prevent one task to accidentally corrupt the memory or the resources used by other

active tasks. This memory area is organized into up to 20 protected areas (12 secure and 8

nonsecure). The MPU regions and registers are banked across secure and nonsecure

states.

The MPU is especially helpful for applications where critical or certified code must be

protected against the misbehavior of other tasks. It is usually managed by an RTOS

(real-time operating system).

If a program accesses a memory location prohibited by the MPU, the RTOS can detect it

and take action. In an RTOS environment, the kernel can dynamically update the MPU area

settings based on the process to be executed.

3.4

Embedded flash memory

The devices feature up to 2 Mbytes of embedded flash memory for storing programs and

data. The flash memory supports a high-cycle data area of up to 100 K cycles.

The flash memory interface features dual-bank operating modes, and read-while-write

(RWW). This allows a read operation to be performed on one bank while an erase or

program operation is performed on the other bank. Each bank contains 128 8-Kbyte pages.

The flash memory embeds a 2-Kbyte OTP (one-time programmable) for user data, and up

to 96 Kbytes supporting high cycling capability (100 K cycles), to use for data (EEPROM

emulation).

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