PXAS30 datasheet(38/52 Pages) PHILIPS

38 / 52 page

Philips Semiconductors

Preliminary specification

XA-S3

XA 16-bit microcontroller

32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),

I2C, 2 UARTs, 16 MB address range

2000 Dec 01

AC ELECTRICAL CHARACTERISTICS (5 V)

VDD = 4.5 V to 5.5 V; Tamb = 0 to +70°C for commercial, Tamb = –40°C to +85°C for industrial.

SYMBOL

FIGURE

PARAMETER

LIMITS

UNIT

SYMBOL

FIGURE

PARAMETER

MIN

MAX

UNIT

External Clock

Oscillator frequency

MHz

Clock period and CPU timing cycle

1/fC

tCHCX

Clock high-time (Note 7)

tC * 0.5

tCLCX

Clock low time (Note 7)

tC * 0.4

tCLCH

Clock rise time (Note 7)

tCHCL

Clock fall time (Note 7)

Address Cycle

tLHLL

26, 28, 30

ALE pulse width (programmable)

(V1 * tC) – 6

tAVLL

26, 28, 30

Address valid to ALE de-asserted (set-up)

(V1 * tC) – 12

tLLAX

26, 28, 30

Address hold after ALE de-asserted

(tC/2) – 10

Code Read Cycle

tPLPH

PSEN pulse width

(V2 * tC) – 10

tLLPL

ALE de-asserted to PSEN asserted

(tC/2) – 7

tAVIVA

Address valid to instruction valid, ALE cycle (access time)

(V3 * tC) – 36

tAVIVB

Address valid to instruction valid, non-ALE cycle (access time)

(V4 * tC) – 29

tPLIV

PSEN asserted to instruction valid (enable time)

(V2 * tC) – 29

tPHIX

Instruction hold after PSEN de-asserted

tPHIZ

Bus 3-State after PSEN de-asserted

tC – 8

tIXUA

Hold time of unlatched part of address after instruction latched

Data Read Cycle

tRLRH

RD pulse width

(V7 * tC) – 10

tLLRL

ALE de-asserted to RD asserted

(tC/2) – 7

tAVDVA

Address valid to data input valid, ALE cycle (access time)

(V6 * tC) – 36

tAVDVB

Address valid to data input valid, non-ALE cycle (access time)

(V5 * tC) – 29

tRLDV

RD low to valid data in (enable time)

(V7 * tC) – 29

tRHDX

Data hold time after RD de–asserted

tRHDZ

Bus 3-State after RD de-asserted (disable time)

tC – 8

tDXUA

Hold time of unlatched part of address after data latched

Data Write Cycle

tWLWH

WR pulse width

(V8 * tC) – 10

tLLWL

ALE falling edge to WR asserted

(V12 * tC) – 10

tQVWX

Data valid before WR asserted (data set-up time)

(V13 * tC) – 22

tWHQX

Data hold time after WR de-asserted (Note 6)

(V11 * tC) – 5

tAVWL

Address valid to WR asserted (address set-up time) (Note 5)

(V9 * tC) – 22

tUAWH

Hold time of unlatched part of address after WR is de-asserted

(V11 * tC) – 7

Wait Input

tWTH

WAIT stable after bus strobe (RD, WR, or PSEN) asserted

(V10 * tC) – 30

tWTL

WAIT hold after bus strobe (RD, WR, or PSEN) asserted

(V10 * tC) – 5

NOTES ON PAGE 41.

PXAS30 Datasheet(PDF) 38 Page - NXP Semiconductors

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