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1389CS–CASIC–06-Nov-06

ATC18 Summary

• Several aspect ratios for optimization

• Separate Data-in, Data-out pins support a write-through feature

• Asynchronous write-through for testing interface shadow logic

•BIST interface

• Optional Sub-word decode

The dual-port synchronous RAM compiler is a high-density RAM compiler with quiescent current

consumption equal to zero when the SRAM is not in a read or write mode. The compiler is opti-

mized for a power supply voltage range of 1.62V to 1.98V and can operate at voltages as low as

1.2V. The SRAM instances can be built with several aspect ratios for maximum area and perfor-

mance optimization. Separate output (Q) and input (D) pins allow a write-through cycle feature.

An asynchronous write-through mode (AWT) allows testing of interface shadow logic through

scan. Built-in BIST interface allows for easy connection to most memBIST solutions. The special

test modes allow externally bypassing read and write self-timed circuits and adjusting read and

write margins. The SRAM compiler also includes a sub-word feature where selective write to

each group of 8-bit sub-words can be done. A maskable write enable signal is provided for each

8-bit group.

Table 7-2 gives the range of permitted dual-port synchronous RAM configurations.

Note:

1. CM = 4, 8, 16: Column Mux option

7.3

Via Programmable ROM

Key features of the via programmable ROM are:

• 1-port high-density synchronous via-2 programmable ROM

• 290 MHz worst-case cycle time (2K x 16) with no limitation on clock duty cycle

• Zero Quiescent Current

• 3-state outputs

• Several aspect ratios for optimization

• Programming support

The via programmable ROM compiler is a high-density low-power synchronous ROM compiler.

The quiescent current consumption is zero when the ROM is not enabled. The compiler is opti-

mized for a power supply voltage range of 1.62V to 1.98V and can operate at voltages as low as

1.26V. The ROM instances can be built with several aspect ratios for maximum area and perfor-

mance optimization. Within limits, the user has flexibility in specifying the logical size of the

ROM, including word size, number of address locations and column mux.

Table 7-2.

Configuration Range

Parameter

Min

Max

Increment

Address Locations (words)

32

8K

Word Size (Number of I/O bits)

2

128

1 bit

Total Bits in Core (Word Size x Address Locations)

128

256K