7

FN2974.3

December 6, 2005

SYMBOL

PARAMETER

LIMITS

UNITS

(NOTE 1)

TEST

CONDITIONS

MIN

MAX

TIMING REQUIREMENTS

(1)

TEHEL

External Frequency HIGH Time

13

-

ns

(2)

TELEH

External Frequency LOW Time

13

-

ns

(3)

TELEL

EFI Period

36

-

ns

XTAL Frequency

2.4

25

MHz

Note 2

(4)

TR2VCL

RDY1, RDY2 Active Setup to CLK

35

-

ns

ASYNC = HIGH

(5)

TR1VCH

RDY1, RDY2 Active Setup to CLK

35

-

ns

ASYNC = LOW

(6)

TR1VCL

RDY1, RDY2 Inactive Setup to CLK

35

-

ns

(7)

TCLR1X

RDY1, RDY2 Hold to CLK

0

-

ns

(8)

TAYVCL

ASYNC Setup to CLK

50

-

ns

(9)

TCLAYX

ASYNC Hold to CLK

0

-

ns

(10)

TA1VR1V

AEN1, AEN2 Setup to RDY1, RDY2

15

-

ns

(11)

TCLA1X

AEN1, AEN2 Hold to CLK

0

-

ns

(12)

TYHEH

CSYNC Setup to EFI

20

-

ns

(13)

TEHYL

CSYNC Hold to EFI

20

-

ns

(14)

TYHYL

CSYNC Width

2 TELEL

-

ns

(15)

TI1HCL

RES Setup to CLK

65

-

ns

Note 3

(16)

TCLI1H

RES Hold to CLK

20

-

ns

Note 3

TIMING RESPONSES

(17)

TCLCL

CLK Cycle Period

125

-

ns

Note 6

(18)

TCHCL

CLK HIGH Time

(1/3 TCLCL) +2.0

-

ns

Note 6

(19)

TCLCH

CLK LOW Time

(2/3 TCLCL) -15.0

-

ns

Note 6

(20)

(21)

TCH1CH2

TCL2CL1

CLK Rise or Fall Time

-

10

ns

1.0V to 3.0V

(22)

TPHPL

PCLK HIGH Time

TCLCL-20

-

ns

Note 6

(23)

TPLPH

PCLK LOW Time

TCLCL-20

-

ns

Note 6

(24)

TRYLCL

Ready Inactive to CLK (See Note 4)

-8

-

ns

Note 4

(25)

TRYHCH

Ready Active to CLK (See Note 3)

(2/3 TCLCL) -15.0

-

ns

Note 5

(26)

TCLIL

CLK to Reset Delay

-

40

ns

(27)

TCLPH

CLK to PCLK HIGH Delay

-

22

ns

(28)

TCLPL

CLK to PCLK LOW Delay

-

22

ns

(29)

TOLCH

OSC to CLK HIGH Delay

-5

22

ns

(30)

TOLCL

OSC to CLK LOW Delay

2

35

ns

NOTES:

2. Tested using EFI or X1 input pin.

3. Setup and hold necessary only to guarantee recognition at next clock.

4. Applies only to T2 states.

5. Applies only to T3 TW states.

6. Tested with EFI input frequency = 4.2MHz.

82C84A

82C84A