R5F104FCAFP datasheet(103/207 Pages) RENESAS

103 / 207 page

RL78/G13

2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)

R01DS0131EJ0350 Rev.3.50

103 of 200

Jun 30, 2020

(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)

(TA = –40 to +85°C, 1.8 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Data setup time

(reception)

tSU:DAT

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 50 pF, Rb = 2.7 k

1/fMCK +

135 Note 3

1/fMCK

+ 190

Note 3

1/fMCK

+ 190

Note 3

kHz

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 50 pF, Rb = 2.7 k

1/fMCK +

135 Note 3

1/fMCK

+ 190

Note 3

1/fMCK

+ 190

Note 3

kHz

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

1/fMCK +

190 Note 3

1/fMCK

+ 190

Note 3

1/fMCK

+ 190

Note 3

kHz

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

1/fMCK +

190 Note 3

1/fMCK

+ 190

Note 3

1/fMCK

+ 190

Note 3

kHz

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note 2,

Cb = 100 pF, Rb = 5.5 k

1/fMCK +

190 Note 3

1/fMCK

+ 190

Note 3

1/fMCK

+ 190

Note 3

kHz

Data hold time

(transmission)

tHD:DAT

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 50 pF, Rb = 2.7 k

305

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 50 pF, Rb = 2.7 k

305

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

355

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

355

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note 2,

Cb = 100 pF, Rb = 5.5 k

405

Notes 1. The value must also be equal to or less than fMCK/4.

2. Use it with EVDD0

≥ Vb.

3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".

Caution

Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 20- to 52-pin

products)/EVDD tolerance (for the 64- to 128-pin products)) mode for the SDAr pin and the N-ch open

drain output (VDD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 128-pin

products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode

(Remarks are listed on the next page.)

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