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R5F104FCAFP Datasheet(PDF) 74 Page - Renesas Technology Corp |
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R5F104FCAFP Datasheet(HTML) 74 Page - Renesas Technology Corp |
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74 / 207 page  RL78/G13 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 74 of 200 Jun 30, 2020 Note The following conditions are required for low voltage interface when EVDD0 < VDD 1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns 1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 2.4 0.03125 0.0625 0.05 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected Supply voltage VDD [V] |
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