R5F104FCAFP datasheet(80/207 Pages) RENESAS

80 / 207 page

RL78/G13

2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)

R01DS0131EJ0350 Rev.3.50

80 of 200

Jun 30, 2020

(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)

(TA = –40 to +85°C, 1.6 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp

↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp

↓”

when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes

“from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. C is the load capacitance of the SCKp and SOp output lines.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin

by using port input mode register g (PIMg) and port output mode register g (POMg).

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SCKp cycle time

tKCY1

≥ 4/fCLK 2.7 V ≤ EVDD0 ≤ 5.5 V

125

500

1000

2.4 V

≤ EVDD0 ≤ 5.5 V

250

500

1000

1.8 V

≤ EVDD0 ≤ 5.5 V

500

1000

1.7 V

≤ EVDD0 ≤ 5.5 V

1000

1.6 V

≤ EVDD0 ≤ 5.5 V

–

1000

SCKp high-/low-level

width

tKH1,

tKL1

4.0 V

≤ EVDD0 ≤ 5.5 V

tKCY1/2 –

2.7 V

≤ EVDD0 ≤ 5.5 V

tKCY1/2 –

2.4 V

≤ EVDD0 ≤ 5.5 V

tKCY1/2 –

1.8 V

≤ EVDD0 ≤ 5.5 V

tKCY1/2 –

1.7 V

≤ EVDD0 ≤ 5.5 V

tKCY1/2 –

100

tKCY1/2 –

100

tKCY1/2 –

100

1.6 V

≤ EVDD0 ≤ 5.5 V

–

tKCY1/2 –

100

tKCY1/2 –

100

SIp setup time

(to SCKp

↑)

Note 1

tSIK1

4.0 V

≤ EVDD0 ≤ 5.5 V

110

2.7 V

≤ EVDD0 ≤ 5.5 V

110

2.4 V

≤ EVDD0 ≤ 5.5 V

110

1.8 V

≤ EVDD0 ≤ 5.5 V

110

1.7 V

≤ EVDD0 ≤ 5.5 V

220

1.6 V

≤ EVDD0 ≤ 5.5 V

–

220

SIp hold time

(from SCKp

↑) Note 2

tKSI1

1.7 V

≤ EVDD0 ≤ 5.5 V

1.6 V

≤ EVDD0 ≤ 5.5 V

–

Delay time from

SCKp

↓ to SOp

output Note 3

tKSO1

1.7 V

≤ EVDD0 ≤ 5.5 V

C = 30 pFNote 4

1.6 V

≤ EVDD0 ≤ 5.5 V

C = 30 pFNote 4

–

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