AM6412...ALV datasheet(172/244 Pages) TI

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SPI_CS[i]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(OUT)

SPI_CS[i]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(OUT)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=0

EPOL=1

POL=0

POL=1

POL=0

POL=1

PHA=1

EPOL=1

SS6

SS3

SS1

SS3

SS1

SS3

SS1

SS2

SS1

SS6

SS8

SS9

SS7

SS8

SS2

SS3

SS2

SS6

SS9

SPRSP08_TIMING_McSPI_03

Figure 7-58. SPI Slave Mode Transmit Timing

7.10.5.12 MMCSD

The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),

and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at

transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking

for syntactical correctness.

For more details about MMCSD interfaces, see the corresponding MMC0 and MMC1 subsections within Signal

Descriptions and Detailed Description sections.

Note

Some operating modes require software configuration of the MMC DLL delay settings, as shown in

Table 7-67 and Table 7-76.

The modes which show a value of "Tuning" in the ITAPDLYSEL column of Table 7-67 and Table 7-76

require a tuning algorithm to be used for optimizing input timing. Refer to the MMCSD Programming

Guide in the device TRM for more information on the tuning algorithm and configuration of input

delays required to optimize input timing.

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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