AM6412...ALV datasheet(141/244 Pages) TI

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Table 7-45. FSI Timing Requirements (continued)

see Figure 7-36

NO.

MIN

MAX

UNIT

FSIR4

th(RX_CLK-RX_D)

Hold time, FSI_RXn_D[1:0] valid after FSI_RXn_CLK

2.5

(1)

P = FSI_RXn_CLK period in ns.

FSI_RXn_CLK

FSIR2

FSIR1

FSIR3

FSI_RXn_D0

FSI_RXn_D1

FSIR4

FSIR2

Figure 7-36. FSI Timing Requirements

Table 7-46. FSI Switching Characteristics - FSI Mode

see Figure 7-37

NO.

PARAMETER

MODE

MIN

MAX

UNIT

FSIT1 tc(TX_CLK)

Cycle time, FSI_TXn_CLK

FSI Mode

FSIT2 tw(TX_CLK)

Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high

FSI Mode

0.5p + 1

(1)

0.5P - 1

(1)

FSIT3 td(TX_CLK-TX_D)

Delay time, FSI_TXn_D[1:0] valid after FSI_TXn_CLK

high or FSI_TXn_CLK low

FSI Mode

0.25P - 2

(1)

0.25P +

2.5

(1)

P = FSI_TXn_CLK period in ns.

FSI_TXn_CLK

FSIT2

FSIT1

FSIT3

FSI_TXn_D0

FSI_TXn_D1

FSIT2

FSIT1

Figure 7-37. FSI Switching Characteristics - FSI Mode

Table 7-47. FSI Switching Characteristics - SPI Mode

see Figure 7-38

NO.

PARAMETER

MODE

MIN

MAX

UNIT

FSIT4 tc(TX_CLK)

Cycle time, FSI_TXn_CLK

SPI Mode

FSIT5 tw(TX_CLK)

Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high

SPI Mode

0.5P + 1

(1)

0.5P - 1

(1)

FSIT6 td(TX_CLKH-TX_D0)

Delay time, FSI_TXn_CLK high to FSI_TXn_D0 valid

SPI Mode

FSIT7 td(TX_D1-TX_CLK)

Delay time, FSI_TXn_D1 low to FSI_TXn_CLK high

SPI Mode

P - 3

(1)

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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