TLV9152SIRUGR datasheet(21/76 Pages) TI

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6.8 Typical Characteristics (continued)

at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)

Temperature (°C)

-40

-20

100

120

140

115

120

125

130

135

140

D023

VS = 4 V

VS = 16 V

Figure 6-25. Open-Loop Voltage Gain vs Temperature (dB)

Frequency (Hz)

150

200

250

300

350

400

450

500

550

600

650

700

100

10k

100k

10M

C013

Figure 6-26. Open-Loop Output Impedance vs Frequency

Cap Load (pF)

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

C007

RISO = 0 , Positive Overshoot

RISO = 0 , Negative Overshoot

RISO = 50 , Positive Overshoot

RISO = 50 , Negative Overshoot

G = –1, 10-mV output step

Figure 6-27. Small-Signal Overshoot vs Capacitive Load

Cap Load (pF)

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

C008

RISO = 0 , Positive Overshoot

RISO = 0 , Negative Overshoot

RISO = 50 , Positive Overshoot

RISO = 50 , Negative Overshoot

G = 1, 10-mV output step

Figure 6-28. Small-Signal Overshoot vs Capacitive Load

Cap Load (pF)

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

C009

Figure 6-29. Phase Margin vs Capacitive Load

Time (20us/div)

C016

Input

Output

VIN = ±8 V; VS = VOUT = ±17 V

Figure 6-30. No Phase Reversal

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TLV9151, TLV9152, TLV9154

SBOS986D – OCTOBER 2019 – REVISED MAY 2021

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