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TLV9152SIRUGR Datasheet(PDF) 8 Page - Texas Instruments |
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TLV9152SIRUGR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 76 page ![]() 1 OUT1 14 OUT4 2 IN1± 13 IN4± 3 IN1+ 12 IN4+ 4 V+ 11 V± 5 IN2+ 10 IN3+ 6 IN2± 9 IN3± 7 OUT2 8 OUT3 Not to scale Figure 5-7. TLV9154 D and PW Package 14-Pin SOIC and TSSOP Top View 1 IN1+ 12 IN4+ 2 V+ 11 V± 3 IN2+ 10 IN3+ 4 IN2± 9 IN3± Not to scale Thermal Pad A. Connect thermal pad to V–. See Packages with and Exposed Thermal Pad for more information. B. Package is preview only. Figure 5-8. TLV9154 RTE Package(A)(B) 16-Pin WQFN With Exposed Thermal Pad Top View 1 IN1± 2 IN1+ 3 V+ 4 IN2+ 5 IN2± 8 IN3± 9 IN3+ 10 V± 11 IN4+ 12 IN4± Not to scale Figure 5-9. TLV9154 RUC Package 14-Pin X2QFN With Exposed Thermal Pad Top View Table 5-5. Pin Functions: TLV9154 PIN I/O DESCRIPTION NAME SOIC, TSSOP WQFN X2QFN IN1+ 3 1 2 I Noninverting input, channel 1 IN1– 2 16 1 I Inverting input, channel 1 TLV9151, TLV9152, TLV9154 SBOS986D – OCTOBER 2019 – REVISED MAY 2021 www.ti.com 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9151 TLV9152 TLV9154 |
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