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TDA3LABBABFQ1 Datasheet(PDF) 98 Page - Texas Instruments |
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TDA3LABBABFQ1 Datasheet(HTML) 98 Page - Texas Instruments |
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98 / 271 page ![]() 98 TDA3MV, TDA3MA, TDA3MD TDA3LX, TDA3LA SPRS964H – JUNE 2016 – REVISED FEBRUARY 2020 www.ti.com Submit Documentation Feedback Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA Specifications Copyright © 2016–2020, Texas Instruments Incorporated Table 5-14. ADC Electrical Specifications (continued) PARAMETER CONDITIONS MIN NOM MAX UNIT Total Harmonic Distortion (THD) 1.8 Vpp, 30 kHz sine wave 60 dB Spurious Free Dynamic Range 1.8 Vpp, 30 kHz sine wave 60 dB Signal-to-Noise Plus Distortion 1.8 Vpp, 30 kHz sine wave 50 dB adc_vrefp Input Impedance 20 Ω Sampling Dynamics Time from Start to Start 17 Clock Cycles Conversion Time + Error Correction 10 + 1 Clock Cycles Acquisition time 4 Clock Cycles Throughput Rate CLK = 20 MHz (Pin : clk) 1 MSPS Channel to Channel Isolation 90 dB ADC Clock Frequency See Table 5-1 MHz (1) Connect adc_vrefp to vdda_adc when not using a positive external reference voltage. (2) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input. (3) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2 ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted digital value. |
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