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STM32L4R9AI Datasheet(PDF) 36 Page - STMicroelectronics

Part # STM32L4R9AI
Description  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, ext. SMPS
PDF  307 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L4R9AI Datasheet(HTML) 36 Page - STMicroelectronics

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Functional overview
STM32L4R5xx, STM32L4R7xx and STM32L4R9xx
36/307
DS12023 Rev 5
3.10.5
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
Independent
watchdog (IWDG)
O
OOO
O
OO
OO
O-
--
Window watchdog
(WWDG)
O
OOO
-
--
--
--
--
SysTick timer
O
O
O
O
-
--
--
--
--
Touch sensing
controller (TSC)
O
OOO
-
--
--
--
--
Random number
generator (RNG)
O(8)
O(8)
--
-
--
--
--
--
CRC calculation
unit
O
OOO
-
--
--
--
--
GPIOs
O
OOO
O
OO
O
(9)
5
pins
(10)
(11)
5
pins
(10)
-
1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off. In Stop 2 mode, the content of SRAM3 is preserved or not depending on the
RRSTP bit in PWR_CR1 register.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
Table 5. Functionalities depending on the working mode(1) (continued)
Peripheral
Run
Sleep
Low-
power
run
Low-
power
sleep
Stop 0/1
Stop 2
Standby Shutdown
VBAT
-
-
-
-



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