STM32L4R9AI datasheet(7/307 Pages) STMICROELECTRONICS

7 / 307 page

DS12023 Rev 5

7/307

STM32L4R5xx, STM32L4R7xx and STM32L4R9xx

List of tables

Table 1.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2.

STM32L4R5xx, STM32L4R7xx and STM32L4R9xx

features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3.

Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19

Table 4.

STM32L4R5xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 5.

Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 6.

STM32L4R5xx, STM32L4R7xx and STM32L4R9xx

peripherals interconnect matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 7.

DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 8.

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 9.

Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 10.

Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 11.

I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 12.

USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 13.

SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 14.

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 15.

STM32L4Rxxx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 16.

Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 17.

Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 18.

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 19.

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 20.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 21.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 22.

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 23.

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 24.

Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 25.

Current consumption in Run and Low-power run modes, code with data

processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . 147

Table 26.

Current consumption in Run and Low-power run modes, code with data processing

running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)

and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 27.

Current consumption in Run and Low-power run modes, code with data

processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF) . . . 149

Table 28.

Consumption in Run and Low-power run modes, code with data processing

running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)

and power supplied by external SMPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 29.

Current consumption in Run and Low-power run modes,

code with data processing running from Flash in single bank, ART disable. . . . . . . . . . . 151

Table 30.

Current consumption in Run and Low-power run modes, code with data processing

running from Flash in single bank, ART disable and power supplied by external SMPS . 152

Table 31.

Current consumption in Run and Low-power run modes,

code with data processing running from Flash in dual bank, ART disable . . . . . . . . . . . . 153

Table 32.

Current consumption in Run and Low-power run modes, code with data processing

running from Flash in dual bank, ART disable and power supplied by external SMPS . . 154

Table 33.

Current consumption in Run and Low-power run modes,

code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 34.

Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1 and power supplied by external SMPS . . . . . . . . . . . . . . . . . . . . . 156

STM32L4R9AI Datasheet(PDF) 7 Page - STMicroelectronics

STM32L4R9AI Datasheet(HTML) 7 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL