USB97C201 datasheet(21/59 Pages) SMSC

21 / 59 page

SMSC DS – USB97C201

Page 21

Rev. 03/25/2002

PRELIMINARY

Table 9 - Interrupt 1 Mask

IMR_1

(0x94- RESET=0xFF)

INTERRUPT 1 MASK REGISTER

BIT

NAME

R/W

DESCRIPTION

ZLP_EP0

R/W

Zero Length Packet Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Resereved

R/W

Reserved. This bit should never be written to a “0”.

ATA_PIO

R/W

ATA PIO Complete Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

EP1RX

R/W

Endpoint 1 Received Packet Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

EP1TX

R/W

Endpoint 1 Transmitted Packet Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

EP0RX

R/W

Endpoint 0 Received Packet Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

EP0TX

R/W

Endpoint 0 Transmitted Packet Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

SUSPEND

R/W

SUSPEND Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Note 1: The mask bits do not prevent the status in the ISR_1 register from being set, only from generating an

interrupt.

Table 10 - Device Revision Register

DEV_REV

(0x95- RESET=0xXX)

DEVICE REVISION REGISTER

BIT

R/W

DESCRIPTION

[7:0]

XXh

This register defines additional revision information

used internally by SMSC. The value is silicon revision

dependent.

Table 11 - Device Identification Register

DEV_ID

(0x96- RESET=0x12)

DEVICE IDENTIFICATION REGISTER

BIT

R/W

DESCRIPTION

[7:0]

12h

This register defines additional revision information

used internally by SMSC

USB97C201 Datasheet(PDF) 21 Page - SMSC Corporation

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