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5220-DS02-R Datasheet(PDF) 59 Page - Broadcom Corporation. |
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5220-DS02-R Datasheet(HTML) 59 Page - Broadcom Corporation. |
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59 / 90 page ![]() Preliminary Data Sheet BCM5220 04/20/04 Broa d c om Co rp o r a t i o n Document 5220-DS04-405-R Auxiliary Mode 2 Register Page 47 Interrupt Mask Master Interrupt Mask. When this bit is set, no interrupts will be generated, regardless of the state of the other MASK bits. FDX Change A 1 indicates a change of Duplex status since last register read. Register read clears the bit. SPD Change A 1 indicates a change of Speed status since last register read. Register read clears the bit. Link Change A 1 indicates a change of Link status since last register read. Register read clears the bit. Interrupt Status Represents status of the INTR# pin. A 1 indicates that the interrupt mask is off and that one or more of the change bits are set. Register read clears the bit. AUXILIARY MODE 2 REGISTER 10BASE-T Dribble Bit Correct When enabled, the PHY rounds down to the nearest nibble when dribble bits are present on the 10BASE-T input stream. Table 26: Auxiliary Mode 2 Register (Address 27d, 1Bh) BIt Name R/W Description Default 15:12 Reserveda RO Ignore when read 0 11 10BASE-T Dribble Bit Correct R/W 1 = Enable, 0 = Disable 0 10 Token Ring Mode R/W 1 = Enable, 0 = Disable 0 9 HSTR FIFO Enable R/W 1 = Enable, 0 = Disable 0 8 Reserveda RO Ignore when read 0 7 Block 10BT Echo Mode R/W 1 = Enable, 0 = Disable 1 6 Traffic Meter LED Mode R/W 1 = Enable, 0 = Disable 0 5 Activity LED Force On R/W 1 = ON, 0 = Normal operation 0 4 Reserveda R/W Ignore when read 1 3 Reserveda R/W Write as 1, Ignore when read 1 2 Activity/Link LED Mode R/W 1 = Enable, 0 = Disable 0 1 Qual Parallel Detect Mode R/W 1 = Enable, 0 = Disable 1 0 Reserveda a. Preserve existing values of reserved bits by completing a “Read/Modify Write.” RO Ignore when read 0 Notes: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after read operation. Use default values of reserved bit(s) when writing to reserved bit(s). |
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