▪ 2, 4, 8, or 16 Low-Power (LP) HCSL outputs saves
up to 64 resistors
▪ 2:N or 2 x 1:N/2 modes (N is number of outputs)
▪ 85Ω or 100Ω output impedance
▪ Outputs drive both source-terminated and doubleterminated
loads
▪ Open-drain LOS output
▪ FPS allows inputs and clocks to be applied before
power is applied or power to be applied with no
input clock
▪ ACP cleanly parks outputs in low/low state when
selected input clock is lost
▪ Spread-spectrum tolerant
▪ Up to eight output enable pins
▪ Selectable 4-wire Side-Band-Interface (SBI) for
hardware output enable (RC19208, RC19216)
▪ SMBus write protection features (RC19216)
▪ CLKIN pins directly support HCSL or LVDS
signaling levels
▪ 3 × 3 mm 20-VFQFPN to 6 × 6 mm 80-VFQFPN packages