Description
The 9DBL0255/9DBL0455 are 2 and 4-output PCIe Clock fan-out
buffers for PCIe Gen1–5 applications. Both parts have an open
drain Loss of Signal (LOS) output to indicate the absence or
presence of an input clock. The LOS circuit also implements
Automatic Clock Parking (ACP) to cleanly park the outputs
low/low when the input clock goes away. The devices implement
several additional features to aid robust designs. Flexible Power
Sequencing (FPS) ensures well-defined behavior under various
power up scenarios, while Power Down Tolerant (PDT) ESD
protection allows input pins to be driven before VDD is applied.
The 9DBL0255/9DBL0455 are spread-spectrum compatible and
provide direct connection to 85Ω transmission lines. They can also
be used in 100Ω environments with simple external series
resistors

Typical Applications
▪ PCIe clock distribution in:
• PCIe Riser Cards
• NVME eSSD and JBOD
• High-Performance Computing and Accelerators

Features
▪ FPS: VDD may be applied with floating input clock, or input
clock may be driven before VDD is applied
▪ ACP: Outputs automatically park low/low when LOS occurs
and cleanly start when LOS is removed
▪ PDT: Input pins may be driven before VDD is applied and will
not damage the device
▪ 2 or 4 Low-power HCSL (LP-HCSL) DIF pairs
▪ 85Ω loads require 0 termination resistors
▪ 100Ω loads require only 2 series resistors per output
▪ OE# pin for each output
▪ Spread-spectrum tolerant
▪ Industrial temperature range (-40°C to +85°C)
▪ Space saving 3 × 3 mm 16-VFQFPN (9DBL0255)
▪ Space saving 4 × 4 mm 20-VFQFPN (9DBL0455)
▪ Easy AC-coupling to other logic families. See application note
AN-891.