Features
• AEC-Q100 automotive qualified
• SR5 high-performance analog MCUs offering:
– Digital and analog high-frequency control requested by new widebandgap
technologies (silicon carbide and gallium nitride)
– Superior real-time and functional safety performance (ASIL-D capability)
– Built-in fast and cost-optimized OTA (over-the-air) reprogramming
capability (with built-in dual-image storage)
– High-speed security cryptographic services (HSM)
Cores
• 2× 32-bit Arm® Cortex®‑M7 with double-precision FPU, L1 cache and DSP
instructions running at up to 300 MHz to reach 1284 DMIPS/2.14 DMIPS/MHz/
core (Dhrystone 2.1)
– Split-lock configuration, allowing either 2 cores in parallel or 1 core in
lockstep configuration
• 2 DMA engines in lockstep configuration
Memories
• Up to 2 MB on-chip flash memory with read while write support
– 1920 KB code flash memory split in two banks allowing 960 KB OTA
reprogramming
– 160 KB HSM dedicated code flash memory
• 96 KB data flash memory (64 KB + 32 KB dedicated to HSM)
• 488 KB on-chip general-purpose SRAM:
– 2× 32 KB instruction TCM + 2× 64 KB data TCM
– 256 KB system RAM
– 40 KB HSM dedicated system RAM
Security: hardware security module (HSM)
• Cybersecurity ISO/SAE 21434 compliance (refer to the cybersecurity reference
manual for details)
• On-chip high-performance security module with EVITA medium support with
dedicated RAM and flash memory
• Based on a Cortex®‑M0+ core running at up to 150 MHz
• Hardware accelerator for symmetric cryptography