Features:

® 4-Stage clocked shift operation

# Synchronous parallel entry on all 4 stages

a JK inputs on first stage

® Asynchronous True/Complement control
on all outputs

® Static flip-flop operation; Master-slave
configuration

® Buffered inputs and outputs

® High speed — 12 MHz (typ.) at Vpp =10V

® 100% tested for quiescent current at 20 V

® Standardized, symmetrical output

characteristics

m 5.V, 10-V, and 15-V parametric ratings

® Meets all requirements of JEDEC Tentative
Standard No. 138, “Standard Specifications
for Description of “B" Series CMOS
Devices”