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D16550 Datasheet (PDF) - Digital Core Design

D16550 Datasheet PDF - Digital Core Design
Part # D16550
Download  D16550 Download

File Size   186.04 Kbytes
Page   7 Pages
Manufacturer  DCD [Digital Core Design]
Direct Link  http://www.digitalcoredesign.com
Logo DCD - Digital Core Design
Description Configurable UART with FIFO ver 2.08

D16550 Datasheet (PDF)

Go To PDF Page Download Datasheet
D16550 Datasheet PDF - Digital Core Design

Part # D16550
Download  D16550 Click to download

File Size   186.04 Kbytes
Page   7 Pages
Manufacturer  DCD [Digital Core Design]
Direct Link  http://www.digitalcoredesign.com
Logo DCD - Digital Core Design
Description Configurable UART with FIFO ver 2.08

D16550 Datasheet (HTML) - Digital Core Design

D16550 Datasheet HTML 1Page - Digital Core Design D16550 Datasheet HTML 2Page - Digital Core Design D16550 Datasheet HTML 3Page - Digital Core Design D16550 Datasheet HTML 4Page - Digital Core Design D16550 Datasheet HTML 5Page - Digital Core Design D16550 Datasheet HTML 6Page - Digital Core Design D16550 Datasheet HTML 7Page - Digital Core Design

D16550 Product details

OVERVIEW
The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-toparallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU.

KEY FEATURES
● Software compatible with 16450 and 16550 UARTs
● Configuration capability
● Separate configurable BAUD clock line
● Two modes of operation: UART mode and FIFO mode
● Majority Voting Logic
● In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU
● Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
● In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
● Independently controlled transmit, receive, line status, and data set interrupts
● False start bit detection
● 16 bit programmable baud generator
● MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
    ○ Fully programmable serial-interface characteristics:
    ○ 5-, 6-, 7-, or 8-bit characters
    ○ Even, odd, or no-parity bit generation and
    ○ 1-, 1½-, or 2-stop bit generation detection
    ○ Baud generation
● Complete status reporting capabilities
● Line break generation and detection. Internal diagnostic capabilities:
    ○ Loop-back controls for communications link fault isolation
    ○ Break, parity, overrun, framing error simulation
● Two DMA Modes allows single and multitransfer
● Technology independent HDL Source Code
● Full prioritized interrupt system controls
● Fully synthesizable static design with no internal tri-state buffers

APPLICATIONS
● Serial Data communications applications
● Modem interface




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About Digital Core Design


Digital Core Design (DCD) is a company that specializes in providing intellectual property (IP) cores for microprocessors and microcontrollers. Founded in 1999 and based in Poland, DCD offers a wide range of IP cores, including 8051, AVR, Z80, 68000, and ARM cores, among others.

DCD's IP cores are used in a variety of applications, including automotive, industrial automation, medical devices, and consumer electronics. The company's IP cores are designed to be highly configurable and customizable, allowing customers to tailor the cores to their specific needs.

In addition to its IP cores, DCD offers a range of design services, including custom microcontroller design, FPGA design, and software development. The company has a team of experienced engineers who work closely with customers to develop custom solutions that meet their specific requirements.

*This information is for general informational purposes only, we will not be liable for any loss or damage caused by the above information.




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