All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

○

○

○

○

●

●

○

○

●

●

●

●

●

●

●

●

●

●

●

●

http://www.DigitalCoreDesign.com

http://www.dcd.pl

1-, 1½-, or 2-stop bit generation

APPLI C ATIONS

Serial Data communications applications

Modem interface

KEY FEATURES

Software compatible with 16450 and

16550 UARTs

Configuration capability

Separate configurable BAUD clock line

Two modes of operation: UART mode and

FIFO mode

Majority Voting Logic

In the FIFO mode transmitter and receiver

are each buffered with 16 byte FIFO to

reduce the number of interrupts presented

to the CPU

Adds or deletes standard asynchronous

communication bits (start, stop, and parity)

to or from the serial data

In UART mode receiver and transmitter

are double buffered to eliminate a need for

precise synchronization between the CPU

and serial data

Independently controlled transmit, receive,

line status, and data set interrupts

False start bit detection

16 bit programmable baud generator

MODEM control functions (CTS, RTS,

DSR, DTR, RI, and DCD)

Fully

programmable

serial-interface

characteristics:

5-, 6-, 7-, or 8-bit characters

Even, odd, or no-parity bit generation and

detection

Baud generation

Complete status reporting capabilities

Line break generation and detection.

Internal diagnostic capabilities:

Loop-back controls for communications link

fault isolation

Break, parity, overrun, framing error

simulation

Two DMA Modes allows single and multi-

transfer

Technology independent HDL Source

Code

Full prioritized interrupt system controls

Fully synthesizable static design with no

internal tri-state buffers

DESIGN FEATURES

The functionality of the D16550 core was

based on the Texas Instruments TL16C550A.

The following characteristics differentiate the

D16550 from Texas Instruments devices:

The bi-directional data bus has been split

into

two

separate

buses:

datai(7:0),

datao(7:0)

Signals rd2 and wr2, xin, and xout have

been removed from interface

Signal ADS and address latch have been

removed

The DLL, DLM and THR registers are

reset to all zeros

TEMT and THRE bits of Line Status

Register, are reset during the second

clock rising edge following a THR write

RCLK clock is replaced by global clock

CLK, internally divided by BAUD factor.

Asynchronous microcontroller interface is

replaced by equivalent Universal interface

All latches implemented in original 16550

devices are replaced by equivalent flip-flop

registers, with the same functionality