ACE24AC64DNTH datasheet(5/17 Pages) ACE

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ACE24AC64

Two-wire Serial EEPROM

VER 1.1

Figure 2: Timing diagram for output ACKNOWLEDGE

Device Addressing

The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to

invoke a valid read or write command. The first four most significant bits of the device address must be

1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These

three device address bits (5

th, 6th and 7th) are to match with the external chip select/address pin states. If a

match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8

th read/write bit,

otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all

device address bits (5

th, 6thand 7th) as noted below. The last or 8th bit is a read/write command bit. If the

8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming

mode.

Write Operations

(A)

BYTE WRITE

A write operation requires two 8-bit data word address following the device address word and

ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then

clock in the first 8-bit data word.

Following receipt of the 8-bit data word, the EEPROM will again

output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence

with

a STOP condition. At this time the EEPROM enters into an internally-timed write cycle state.

All inputs

are disabled during this write cycle and the EEPROM will not respond until the writing is

completed (figure 3).

ACE24AC64DNTH Datasheet(PDF) 5 Page - ACE Technology Co., LTD.