THS1040

SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004

6

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electrical characteristics

over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),

differential input range = 1 VPP and 2 VPP, TA = Tmin to Tmax (unless otherwise noted) (continued)

dynamic performance (ADC)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ENOB

Effective number of bits

f = 4.8 MHz, −0.5 dBFS

8.8

9.6

Bits

ENOB

Effective number of bits

f = 20 MHz, −0.5 dBFS

9.5

Bits

SFDR

Spurious free dynamic range

f = 4.8 MHz, −0.5 dBFS

60.5

72

dB

SFDR

Spurious free dynamic range

f = 20 MHz, −0.5 dBFS

70

dB

THD

Total harmonic distortion

f = 4.8 MHz, −0.5 dBFS

− 72.5

− 61.3

dB

THD

Total harmonic distortion

f = 20 MHz, −0.5 dBFS

− 71.6

dB

SNR

Signal-to-noise ratio

f = 4.8 MHz, −0.5 dBFS

55.7

60

dB

SNR

Signal-to-noise ratio

f = 20 MHz, −0.5 dBFS

57

dB

SINAD

Signal-to-noise and distortion

f = 4.8 MHz, −0.5 dBFS

55.6

59.7

dB

SINAD

Signal-to-noise and distortion

f = 20 MHz, −0.5 dBFS

59.6

dB

BW

Full power bandwidth (−3 dB)

900

MHz

digital specifications

PARAMETER

MIN

NOM

MAX

UNIT

Digital Inputs

VIH

High-level input voltage

Clock input

0.8

× AVDD

V

VIH

High-level input voltage

All other inputs

0.8

× DVDD

V

VIL

Low-level input voltage

Clock input

0.2

× AVDD

V

VIL

Low-level input voltage

All other inputs

0.2

× DVDD

V

IIH

High-level input current

1

µA

IIL

Low-level input current

|−1|

µA

Ci

Input capacitance

5

pF

Digital Outputs

VOH

High-level output voltage

Iload = 50 µA

DVDD−0.4

V

VOL

Low-level output voltage

Iload = −50 µA

0.4

V

High-impedance output current

±1

µA

Rise/fall time

Cload = 15 pF

3.5

ns

Clock Input

tc

Clock cycle time

25

200

ns

tw(CKH)

Pulse duration, clock high

11.25

110

ns

tw(CKL)

Pulse duration, clock low

11.25

110

ns

Clock duty cycle

45%

50%

55%

td(o)

Clock to data valid, delay time

9.5

16

ns

Pipeline latency

4

Cycles

td(AP)

Aperture delay time

0.1

ns

Aperture uncertainty (jitter)

1

ps

timing

PARAMETER

MIN

TYP

MAX

UNIT

td(DZ)

Output disable to Hi-Z output, delay time

0

10

ns

td(DEN)

Output enable to output valid, delay time

0

10

ns

VO(BIASREF) Output voltage

MODE = AVDD

(AVDD/2) − 0.1

(AVDD/2) + 0.1

V