ADL5565ACPZ-R7 datasheet(19/29 Pages) AD

19 / 29 page

ADL5565

Data Sheet

INPUT AND OUTPUT INTERFACING

The ADL5565 can be configured as a differential input to

differential output driver, as shown in Figure 32. The resistors,

R1 and R2, combined with the ETC1-1-13 balun transformer,

provide a 50 Ω input match for the three input impedances that

change with the variable gain strapping. The input and output

0.1 µF capacitors isolate the VCC/2 bias from the source and

balanced load. The load should equal 200 Ω to provide the

expected ac performance (see the Specifications section and the

Typical Performance Characteristics section).

3V TO 5V

VIP2

VIP1

VIN1

VIN2

Ω

0.1µF

ETC1-1-13

0.1µF

NOTES

1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1.

2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2.

3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2

AND INPUT B TO BOTH VIN1 AND VIN2.

Figure 32. Differential Input to Differential Output Configuration

Table 6. Differential Termination Values for Figure 32

Gain (dB)

R1 (Ω)

R2 (Ω)

15.5

40.2

The differential gain of the ADL5565 is dependent on the

source impedance and load, as shown in Figure 33.

100

Ω

200

Ω

200

Ω

100

Ω

VIP2

VIP1

VIN1

VIN2

Ω

1/2 RS

0.1µF

Figure 33. Differential Input Loading Circuit

The differential gain can be determined using the following

formula. The values of RG for each gain configuration are shown

in Table 7.

200

(1)

In Equation 1, RG is the gain setting resistor (see Figure 1).

Table 7. Values of RG for Differential Gain

Gain (dB)

RG (Ω)

100

15.5

33.5

Single-Ended Input to Differential Output

The ADL5565 can also be configured in a single-ended input

to differential output driver, as shown in Figure 34. In this

configuration, the gain of the part is reduced due to the application

of the signal to only one side of the amplifier. The strappable

gain values are listed in Table 8 with the required terminations

to match to a 50 Ω source using R1 and R2. The input and output

0.1 µF capacitors isolate the VCC/2 bias from the source and the

balanced load. The performance for this configuration is shown

in Figure 16 and Figure 21.

VIP2

VIP1

VIN1

VIN2

Ω

0.1µF

3V TO 5V

NOTES

1. FOR 5.3dB GAIN (AV = 1.84), CONNECT INPUT A TO VIP1

AND INPUT B TO VIN1.

2. FOR 10.3dB GAIN (AV = 3.3), CONNECT INPUT A TO VIP2

AND INPUT B TO VIN2.

3. FOR 13dB GAIN (AV = 4.5), CONNECT INPUT A TO BOTH

VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.

0.1µF

Figure 34. Single-Ended Input to Differential Output Configuration

Table 8. Single-Ended Termination Values for Figure 34

Gain (dB)

R1 (Ω)

R2 (Ω)

5.3

10.3

104

154

The single-ended gain configuration of the ADL5565 is dependent

on the source impedance and load, as shown in Figure 35.

200

Ω

200

Ω

VIP2

VIP1

VIN1

VIN2

Ω

0.1µF

100

Ω

100

Ω

Figure 35. Single-Ended Input Loading Circuit

Rev. E | Page 18 of 28

ADL5565ACPZ-R7 Datasheet(PDF) 19 Page - Analog Devices

ADL5565ACPZ-R7 Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL