R5F104FKA datasheet(100/213 Pages) RENESAS

100 / 213 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85

°C)

R01DS0053EJ0330 Rev. 3.30

Page 100 of 208

Aug 12, 2016

Note

Use it with EVDD0

≥ Vb.

Caution

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin

products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port

input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics

with TTL input buffer selected.

(Remarks are listed two pages after the next page.)

(8)

Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output)

(TA = -40 to +85°C, 1.8 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) mode

LS (low-speed main)

mode

LV (low-voltage

main) mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SCKp cycle time

tKCY1

≥ 4/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

300

1150

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

500

1150

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note,

Cb = 30 pF, Rb = 5.5 k

1150

SCKp high-level

width

tKH1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2 - 75

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2 - 170

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2 - 458

SCKp low-level

width

tKL1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2 - 12

tKCY1/2 - 50

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2 - 18

tKCY1/2 - 50

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2 - 50

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