BQ40Z50-R2 datasheet(34/51 Pages) TI1

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nd Level Protector

to FUSE Pin

bq40z50-R2

SLUSCS4 – JUNE 2017

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The SMBus clock and data lines have internal pulldown. When the gas gauge senses that both lines are low

(such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP

mode to conserve power.

Figure 30. ESD Protection for SMBus Communication

9.2.2.2.5

FUSE Circuitry

The FUSE pin of the bq40z50-R2 device is designed to ignite the chemical fuse if one of the various safety

criteria is violated. The FUSE pin also monitors the state of the secondary-voltage protection IC. Q5 ignites the

chemical fuse when its gate is high. The 7-V output of the bq294700 is divided by R18 and R19, which provides

adequate gate drive for Q5 while guarding against excessive back current into the bq294700 if the FUSE signal

is high.

Using C7 is generally a good practice, especially for RFI immunity. C7 may be removed, if desired, because the

chemical fuse is a comparatively slow device and is not affected by any sub-microsecond glitches that come from

the FUSE output during the cell connection process.

If the AFEFUSE output is not used, it should be connected to VSS.

Figure 31. FUSE Circuit

When the bq40z50-R2 device is commanded to ignite the chemical fuse, the FUSE pin activates to give a typical

8-V output. The new design makes it possible to use a higher Vgs FET for Q5. This improves the robustness of

the system, as well as widens the choices for Q5.

9.2.2.3 Secondary-Current Protection

The bq40z50-R2 device provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage

multiplexing, and voltage translation. The following section examines cell and battery inputs, pack and FET

control, temperature output, and cell balancing.

BQ40Z50-R2 Datasheet(PDF) 34 Page - Texas Instruments