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74ACT1284 Datasheet(PDF) 1 Page - STMicroelectronics |
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74ACT1284 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 11 page  1/11 July 2003 s HIGH SPEED: TPD = 6.5 ns (Max. 85°C) at VCC =4.5V s LOW POWER DISSIPATION: ICC = 80 µA (MAX.) at VCC =5.5V T = 85 °C s TTL COMPATIBLE INPUTS VIH =2V (Min.) VIL =0.8V (Max.) s OPERATING VOLTAGE RANGE: VCC (OPR.) = 4.5V to 5.5V s A Port have standard 4mA totem pole output s B Port high drive source/sink capability of 14mA s Support IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) for bidirectional parallel communications between personal computer and printing peripherals. DESCRIPTION The 74ACT1284 contains four high-speed non-in- verting bidirectional buffers and three non-invert- ing buffers with open drain outputs fabricated in silicon gate C2MOS technology. It’s intended to provide a standard signaling meth- od for a bidirection parallel peripheral in an Ex- tended Capabilities Port mode (ECP). The HD (active High) input pin enables the B ports to switch from Open Drain to a high drive totem pole output, capable of sourcing 14mA on all sev- en buffers. The DIR input determines the direction of data flow on the bidirectional buffers. DIR (active High) enables data flow from A Port to B Port. DIR (active Low) enables data flow from B Port to A Port. ESD protection is greater than 2000V per Method 3015.7 of MIL-STD-883B. It’s available in the commercial temperature ranges. 74ACT1284 HIGH SPEED IEEE1284 TRANSCEIVER ORDER CODES PACKAGE TUBE T & R SOP 74ACT1284M 74ACT1284MTR TSSOP 74ACT1284TTR TSSOP SOP PIN CONNECTION |
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