STK14CA8

December 2004

Document Control #ML0022 rev 1.0

2

G

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

W

HSB

E

32 Pin

SOIC

or PDIP

48 Pin SSOP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

W

HSB

G

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

E

PACKAGES

PIN DESCRIPTIONS

Pin Name

I/O

Description

Input

Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.

I/O

Data: Bi-directional 8-bit data bus for accessing the nvSRAM.

E

Input

Chip Enable: The active low E

input selects the device.

W

Input

Write Enable: The active low W

enables data on the DQ pins to be written to the address location latched by

the falling edge of E .

G

Input

Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G

high causes the DQ pins to tri-state.

Power Supply

Power 3.0V +20%, -10%

HSB

I/O

Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external

to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not

connected. (Connection Optional)

Power Supply

Autostore

Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile

elements.

Power Supply

Ground

(Blank)

No Connect

Unlabeled pins have no internal connection.

Relative PCB area usage.

See website for detailed

package size specifications.