SMSC DS – PPC34C60

Page 3

Rev. 06/01/2001

ADVANCED INFORMATION

TABLE OF CONTENTS

1

PIN CONFIGURATION ..........................................................................................................................................4

1.1

Buffer Type Descriptions...........................................................................................................................11

1.2

General Conventions .................................................................................................................................11

1.3

Reference Documents ...............................................................................................................................11

2

PPC34C60 BLOCK DESCRIPTION ....................................................................................................................12

3

DAISY CHAIN COMMAND PROTOCOL.............................................................................................................13

3.1

Peripheral System Design .........................................................................................................................14

3.2

Design Example .........................................................................................................................................15

3.3

Device Addressing.....................................................................................................................................16

3.4

Internal Register Map.................................................................................................................................18

4

REGISTER DESCRIPTIONS ...............................................................................................................................19

5

DRAM BUFFER OPERATION.............................................................................................................................29

5.1

Dram Physical Addressing........................................................................................................................30

6

SYSTEM DATA BUS CYCLES ...........................................................................................................................31

7

OPERATIONAL DESCRIPTION..........................................................................................................................34

8

TIMING DIAGRAMS ............................................................................................................................................36

8.1

DMA Transfer Cycle Timing ......................................................................................................................57