TLH5066 – 27

(a) Resistive Divider with

Decoupling Capaciter

TLH5066 – 28

(b) Voltage Regulator

TLH5066 – 29

(c) Operational Amplifier

with Divider

FIGURE 18 Three Ways of Generating

V

a

2

for Single-supply Operation

For a cutoff frequency of 200 Hz the external clock can be

Logic Level Shift pin (7) determines the logic threshold for

the clock input The threshold is approximately 2V higher

than the voltage applied to pin 7 Therefore when pin 7 is

grounded the clock logic threshold will be 2V making it

CMOS levels Pin 7 should be connected to a clean low-im-

pedance (less than 1000X) voltage source

The complete circuit of the design example is shown for a

1001 clock ratio in

Figure 16

32 SINGLE SUPPLY OPERATION

The MF5 can also operate with a single-ended power sup-

ply

Figure 17 shows the example filter with a single-ended

This half-supply point should be very ‘‘clean’’ as any noise

appearing on it will be treated as an input to the filter It can

be derived from the supply voltage with a pair of resistors

and a bypass capacitor (

Figure 18a ) or a low-impedance

half-supply voltage can be made using a three-terminal volt-

age regulator or an operational amplifier (

Figures 18b and

18c ) The passive resistor divider with a bypass capacitor is

sufficient for many applications provided that the time con-

stant is long enough to reject any power supply noise It is

also important that the half-supply reference present a low

impedance to the clock frequency so at very low clock fre-

quencies the regulator or op-amp approaches may be pref-

erable because they will require smaller capacitors to filter

the clock frequency The main power supply voltage should

be clean (preferably regulated) and bypassed with 01mF

33 DYNAMIC CONSIDERATIONS

The maximum signal handling capability of the MF5 like

that of any active filter is limited by the power supply volt-

ages used The amplifiers in the MF5 are able to swing to

within about 1 volt of the supplies so the input signals must

be kept small enough that none of the outputs will exceed

voltage multiplied by the filter gain should therefore be less

Note that if the filter has high Q the gain at the lowpass or

highpass outputs will be much greater than the nominal filter

gain (

Figure 6 ) As an example a lowpass filter withaQof

volt supplies

Also note that one output can have a reasonable small volt-

age on it while another is saturated This is most likely for a

circuit such as the notch in Mode 1 (

Figure 7 ) The notch

apply a large signal to the input However the bandpass will

output clips the performance at the other outputs will be

degraded so avoid overdriving any filter section even ones

whose outputs are not being directly used Accompanying

Figures 7 through 15 are equations labeled ‘‘circuit dynam-

ics’’ which relate the Q and the gains at the various outputs

These should be consulted to determine peak circuit gains

and maximum allowable signals for a given application

34 OFFSET VOLTAGE

The MF5’s switched capacitor integrators have a higher

equivalent input offset voltage than would be found in a

typical continuous-time active filter integrator

Figure 19

shows an equivalent circuit of the MF5 from which the out-

put dc offsets can be calculated Typical values for these

offsets are

501

b

310mV

1001

501

a

240mV

1001

The dc offset at the BP output is equal to the input offset of

puts depend on the mode of operation and the resistor ra-

tios as described in the following expressions

13