STM32F437II datasheet(38/240 Pages) STMICROELECTRONICS

38 / 240 page

Functional overview

STM32F437xx and STM32F439xx

38/240

DocID024244 Rev 10

3.26

Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be

operated in master or slave mode, in full duplex and simplex communication modes, and

can be configured to operate with a 16-/32-bit resolution as an input or output channel.

Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of

the I2S interfaces is/are configured in master mode, the master clock can be output to the

external DAC/CODEC at 256 times the sampling frequency.

All I2Sx can be served by the DMA controller.

Note:

For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port

B and GPIO Port D.

3.27

Serial Audio interface (SAI1)

The serial audio interface (SAI1) is based on two independent audio sub-blocks which can

operate as transmitter or receiver with their FIFO. Many audio protocols are supported by

each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF

output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks

can be configured in master or in slave mode.

In master mode, the master clock can be output to the external DAC/CODEC at 256 times of

the sampling frequency.

The two sub-blocks can be configured in synchronous mode when full-duplex mode is

required.

SAI1 can be served by the DMA controller.

3.28

Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows

to achieve error-free I2S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change

without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the

I2S/SAI flow with an external PLL (or Codec output).

3.29

Audio and LCD PLL(PLLSAI)

An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the

PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or

11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.

The PLLSAI is also used to generate the LCD-TFT clock.

STM32F437II Datasheet(PDF) 38 Page - STMicroelectronics

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