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PL500-15SC-R Datasheet(PDF) 2 Page - Micrel Semiconductor

Part # PL500-15SC-R
Description  Low Phase Noise VCXO (1MHz to 18MHz)
PDF  5 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

PL500-15SC-R Datasheet(HTML) 2 Page - Micrel Semiconductor

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PL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 7/01/10 Page 2
DIE PAD LAYOUT
DIE SPECIFICAT IONS
Name
Value
Size
39 x 32 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
8 mil
DIE PAD ASSIGNMENT
Name
Pin#
Die Pad Position
Type
Description
SOP-8
SOT23-6
X (
m)
Y (
m)
XIN
1
3
94.183
768.599
I
Crystal input pin.
VCON
2
1
94.157
605.029
P
Frequency Control Voltage input pin.
DIVSEL
3
-
94.183
331.756
I
Divider Selection input pin. Default Logic 1 for
SOT23 package. See Divider Selection Logic
Levels table on Page 1.
GND
4
2
94.193
140.379
P
Ground pin.
CLK
5
6
715.472
203.866
O
Output clock pin.
VDD
6
5
715.307
455.726
P
VDD power supply pin.
OE
7
-
715.472
626.716
I
Output Enable input pin. Disables the output
when low. Internal pull-up enables output by
default if pin is not connected to low. Default
“Enabled” (Logic 1) for SOT23 package.
XOUT
8
4
476.906
888.881
I
Crystal output pin.
5
Y
X
(0,0)
(812,986)
32 mil
8
6
2
3
4
7
DIE ID: PL500-15: C500A-1111-12
PL500-16: C500A-1111-11
1 XIN
DIVSEL^
CLK
GND
VCON
XOUT
OE^
VDD
Note: ^ denotes internal pull up



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