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PCA9554TS Datasheet(PDF) 12 Page - NXP Semiconductors |
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PCA9554TS Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 20 page  Philips Semiconductors Product data sheet PCA9554/PCA9554A 8-bit I2C and SMBus I/O port with interrupt 2004 Sep 30 12 SDA SCL SU01469 tHD;STA tF S tLOW tR tHD;DAT tSU;DAT tHIGH tF tSU;STA SR tHD;STA tSP tSU;STD P tR tBUF S Figure 12. Definition of timing AC SPECIFICATIONS SYMBOL PARAMETER STANDARD MODE I2C-BUS FAST MODE I2C-BUS UNITS MIN MAX MIN MAX fSCL Operating frequency 0 100 0 400 kHz tBUF Bus free time between STOP and START conditions 4.7 — 1.3 — µs tHD;STA Hold time after (repeated) START condition 4.0 — 0.6 — µs tSU;STA Repeated START condition setup time 4.7 — 0.6 — µs tSU;STO Setup time for STOP condition 4.0 — 0.6 — µs tHD;DAT Data in hold time 0 — 0 — ns tVD;ACK Valid time for ACK condition2 0.3 3.45 0.1 0.9 µs tVD;DAT Data out valid time3 300 — 50 — ns tSU;DAT Data setup time 250 — 100 — ns tLOW Clock LOW period 4.7 — 1.3 — µs tHIGH Clock HIGH period 4.0 — 0.6 — µs tF Clock/Data fall time — 300 20 + 0.1 Cb1 300 ns tR Clock/Data rise time — 1000 20 + 0.1 Cb1 300 ns tSP Pulse width of spikes that must be suppressed by the input filters — 50 — 50 ns Port Timing tPV Output data valid — 200 — 200 ns tPS Input data setup time 100 — 100 — ns tPH Input data hold time 1 — 1 — µs Interrupt Timing tIV Interrupt valid — 4 — 4 µs tIR Interrupt reset — 4 — 4 µs NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. |
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