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UCD3138RMHT Datasheet(PDF) 21 Page - Texas Instruments |
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UCD3138RMHT Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 78 page  DPWM PCM ADC12 PMBUS TIMER CPCC FILTER SCI SCI GIO FE_CTRL 0 1 2 3 4 5 6 UCD3138 Function G001 4.9 2.57 1.2 0.8 0.4 0.4 0.2 0.2 0.1 0.1 0 UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 3.7 Typical Clock Gating Power Savings Power disable control register provides control bits that can enable or disable arrival of clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more. All these controls are enabled as default. If a specific peripheral is not used in a specific application the clock gate can be disabled in order to block the propagation of clock signal to that peripheral and therefore reduce the overall current consumption of the device. Copyright © 2012–2013, Texas Instruments Incorporated Electrical Specifications 21 Submit Documentation Feedback Product Folder Links: UCD3138 |
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