quired at the serial data input to the µP. For example,

Motorola’s MC68HC11A8 data book specifies a 100ns

minimum data-setup time. Using the worst case for a

Characteristics) and substituting in the above equation

indicates a maximum SCLK frequency of 1.3MHz.

Using the MAX191 with SPI, QSPI and

MICROWIRE Serial Interfaces

Figure 13 shows interface connections to the MAX191

for common serial-interface standards.

SPI and MICROWIRE (CPOL=0, CPHA=0)

The MAX191 is compatible with SPI, QSPI and

MICROWIRE serial-interface standards. When using SPI

or QSPI, two modes are available to interface with the

MAX191. You can set CPOL = 0 and CPHA = 0 (Figure

14a), or set CPOL = 1 and CPHA = 1 (Figure 14b). When

using CPOL = 0 and CPHA = 0, the conversion begins

on the first falling edge of SCLK following CS going low.

Data is available from DOUT on the rising edge of SCLK,

and transitions on the falling edge. Two consecutive

1-byte reads are required to get the full 12 bits from the

ADC. The first byte contains the following, in this order: a

leading unknown bit (DOUT will still be high-impedance

on the first bit), a 0, and the six MSBs. The second byte

contains the remaining six LSBs and two trailing 0s.

SPI (CPOL=1, CPHA=1)

Setting CPOL = 1 and CPHA = 1 starts the clock high

during a read instruction. The MAX191 will shift out a

leading 0 followed by the 12 data bits and three trailing

0s (Figure 14b).

QSPI

Unlike SPI, which requires two 1-byte reads to acquire

the 12 bits of data from the ADC, QSPI allows the mini-

mum number of clock cycles required to clock in the

data (Figure 15).

TMS320 Serial Interface

Figure 13d shows the pin connections to interface the

MAX191 to the TMS320. Since the MAX191 makes data

available on the rising edge of SCLK and the TMS320

shifts data in on the falling edge of CLKR, use CLKX of the

DSP to drive SCLK, and CLKX to drive the DSP’s CLKR

input. The inverter’s propagation delay also provides more

data-setup time at the DSP. For example, with no inverter

available setup time before the SCLK transition is:

This still exceeds the 13ns minimum DR setup time before

the CLKR goes low (tsu(DR)), however, a generic 74HC04

provides an additional 20ns setup time (see Figure 13d).

Figure 16 shows the DSP interface timing characteris-

tics. The DSP begins clocking data in on the falling

edge of CLKR after the falling edge of SSTRB.

Low-Power, 12-Bit Sampling ADC

with Internal Reference and Power-Down

16

______________________________________________________________________________________

DOUT

LEADING

ZERO

MSB

D9

D10

D7

D8

D5

D6

D3

D4

D1

D2

LSB

CS

SCLK

HIGH-Z

1ST BYTE READ

2ND BYTE READ

HIGH-Z

a. CPOL = 0, CPHA = 0

DOUT

LEADING

ZERO

MSB

D9

D10

D7

D8

D5

D6

D3

D4

D1

D2

LSB

CS

SCLK

HIGH-Z

HIGH-Z

b. CPOL = 1, CPHA = 1

Figure 14. SPI/MICROWIRE Serial-Interface Timing