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CTL0422PS-R3 Datasheet(PDF) 1 Page - CT Micro International Corporation |
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CTL0422PS-R3 Datasheet(HTML) 1 Page - CT Micro International Corporation |
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1 / 11 page ![]() CT Micro Rev 1 Proprietary & Confidential Page 1 Nov, 2013 CTL0422PS-R3 P-Channel Enhancement MOSFET Package Outline Schematic Features Drain-Source Breakdown Voltage VDSS -20 V Drain-Source On-Resistance RDS(ON) 45m , at V GS = -4.5V, ID= -4.0A RDS(ON) 52m , at V GS = -2.5V, ID= -3.0A RDS(ON) 60m , at V GS = -1.8V, ID= -2.0A Continuous Drain Current at TC=25℃ ID = -4.0A Advanced high cell density Trench Technology RoHS Compliance & Halogen Free Applications Power Management Lithium Ion Battery Description The CTL0422PS-R3 is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching and low in-line power loss are needed in a very small outline surface mount package. Gate Source Drain Gate Drain Source |
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