MB9AF142LB datasheet(95/121 Pages) SPANSION

95 / 121 page

D a t a S h e e t

MB9A140NB_DS706-00040-4v0-E, June 10, 2015

CONFIDENTIAL

5. 12-bit A/D Converter

 Electrical Characteristics for the A/D Converter

(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)

Parameter

Symbol

name

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Integral Nonlinearity

± 2

± 4.5

LSB

Differential

Nonlinearity

± 2.2

± 2.5

LSB

Zero transition voltage

VZT

ANxx

± 6

± 15

Full-scale transition

voltage

VFST

ANxx

AVRH ± 6 AVRH ± 15

Conversion time

2.0*

μs

AVCC ≥ 2.7 V

4.0*

1.8 V< AVCC < 2.7 V

10*

1.65 V< AVCC < 1.8 V

Sampling time*

0.6

AVCC ≥ 2.7 V

1.2

1.8 V< AVCC < 2.7 V

3.0

1.65 V< AVCC < 1.8 V

Compare clock

cycle*

tCCK

100

1000

AVCC ≥ 2.7 V

200

1.8 V< AVCC < 2.7 V

500

1.65 V< AVCC < 1.8 V

State transition time to

operation permission

tSTT

1.0

μs

Power supply current

(analog + digital)

AVCC

0.27

0.42

A/D 1unit operation

0.03

μA

When A/D stops

Reference power

supply current

(between AVRH to

AVSS)

AVRH

0.72

1.29

A/D 1unit operation

AVRH=3.6 V

0.02

2.6

μA

When A/D stops

Analog input capacity

CAIN

9.4

Analog input resistor

RAIN

2.2

kΩ

AVCC ≥ 2.7 V

5.5

1.8 V< AVCC < 2.7 V

10.5

1.65 V< AVCC < 1.8 V

Interchannel disparity

LSB

Analog port input

current

ANxx

μA

Analog input voltage

ANxx

AVSS

AVRH

Reference voltage

AVRH

2.7

AVCC

AVCC ≥ 2.7 V

AVCC

AVCC < 2.7 V

*1: The conversion time is the value of sampling time (tS) + compare time (tC).

The condition of the minimum conversion time is the following.

AVCC ≥ 2.7 V, HCLK=40 MHz

sampling time: 0.6 μs, compare time: 1.4 μs

1.8 V < AVCC < 2.7 V, HCLK=40 MHz

sampling time: 1.2 μs, compare time: 2.8 μs

1.65 V < AVCC < 1.8 V, HCLK=40 MHz

sampling time: 3 μs, compare time: 7 μs

Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).

For setting of the sampling time and the compare clock cycle, see Chapter 1-1: A/D Converter in FM3

Family Peripheral Manual Analog Macro Port.

The register setting of the A/D Converter are reflected in the operation according to the APB bus clock

timing.

The sampling clock and compare clock is generated from the Base clock (HCLK).

About the APB bus number which the A/D Converter is connected to, see  Block Diagram in this data

sheet.

*2: A necessary sampling time changes by external impedance.

Ensure that it set the sampling time to satisfy (Equation 1).

*3: The compare time (tC) is the value of (Equation 2).

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