74F164ASC datasheet(2/8 Pages) NSC

2 / 8 page

Connection Diagrams

Pin Assignment for

DIP SOIC and Flatpak

TLF10613 – 2

Pin Assignment

for LCC

TLF10613 – 3

Unit LoadingFan Out

54F74F

Pin Names

Description

Input IIH IIL

HIGHLOW

Output IOH IOL

A B

Data Inputs

1010

20 mA b06 mA

Clock Pulse Input (Active Rising Edge)

1010

20 mA b06 mA

Master Reset Input (Active LOW)

1010

20 mA b06 mA

Q0–Q7

Outputs

50333

1 mA20 mA

Functional Description

The ’F164A is an edge-triggered 8-bit shift register with seri-

al data entry and an output from each of the eight stages

Data is entered serially through one of two inputs (A or B)

either of these inputs can be used as an active HIGH En-

able for data entry through the other input An unused input

must be tied HIGH

Each LOW-to-HIGH transition on the Clock (CP) input shifts

data one place to the right and enters into Q0 the logical

AND of the two data inputs (A

B) that existed before the

rising clock edge A LOW level on the Master Reset (MR)

input overrides all other inputs and clears the register asyn-

chronously forcing all Q outputs LOW

Mode Select Table

Operating

Inputs

Outputs

Mode

ABQ0

Q1–Q7

Reset (Clear)

L-L

q0–q6

Shift

q0–q6

H(h) e HIGH Voltage Levels

L(l) e LOW Voltage Levels

X e Immaterial

qn e Lower case letters indicate the state of the referenced input or output

one setup time prior to the LOW-to-HIGH clock transition

Logic Diagram

TLF10613 – 5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

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