UC184xA/284xA/384xA

PRODUCT DA T ABOOK 1996/1997

7

Copyright © 1995

Rev. 1.2

12/95

TYPICAL APPLICA TION CIRCUITS

(continued)

FIGURE 6. — SLOPE COMPENSATION

FIGURE 7. — OPEN LOOP LABORATORY FIXTURE

2

3

4

8

7

6

5

COMP

V

FB

I

SENSE

R

V

REF

V

CC

OUTPUT

GROUND

0.1µF

0.1µF

A

UCx84xA

R

T

2N2222

100K

4.7K

1K

4.7K

5K

I

SENSE

ADJUST

ERROR AMP

ADJUST

C

T

1K

GROUND

OUTPUT

V

CC

V

REF

1

OSCILLATOR

V

REF

GOOD LOGIC

S

R

5V

REF

INTERNAL

BIAS

8(14)

4(7)

2(3)

1(1)

R

F

C

F

R

d

R

i

From V

O

R

SLOPE

2N222A

R

T

5V

UVLO

2.5V

ERROR

AMP

C

T

1V

2R

R

C.S.

COMP

PWM

LATCH

5(9)

3(5)

5(8)

CR

S

R

6(10)

7(11)

7(12)

V

CC

DC BUS

V

O

Q1

UCx84xA

Due to inherent instability of current mode converters running above 50% duty cycle, slope compensation should be added to either

the current sense pin or the error amplifier. Figure 6 shows a typical slope compensation technique.

High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be

connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an

adjustable ramp to pin 3.