LT1376CS datasheet(23/28 Pages) LINER

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LT1375/LT1376

APPLICATIONS INFORMATION

Keep in mind that this procedure does not take initial

component tolerance into account. You should see fairly

clean response under all load and line conditions to ensure

that component variations will not cause problems. One

note here: according to Murphy, the component most

likely to be changed in production is the output capacitor,

because that is the component most likely to have manu-

facturer variations (in ESR) large enough to cause prob-

lems. It would be a wise move to lock down the sources of

the output capacitor in production.

A possible exception to the “clean response” rule is at very

light loads, as evidenced in Figure 17 with ILOAD = 50mA.

Switching regulators tend to have dramatic shifts in loop

response at very light loads, mostly because the inductor

current becomes discontinuous. One common result is

very slow but stable characteristics. A second possibility

is low phase margin, as evidenced by ringing at the output

with transients. The good news is that the low phase

margin at light loads is not particularly sensitive to com-

ponent variation, so if it looks reasonable under a transient

test, it will probably not be a problem in production. Note

that

frequency of the light load ringing may vary with

component tolerance but phase margin generally hangs in

there.

THERMAL CALCULATIONS

Power dissipation in the LT1376 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current, and input quiescent current. The following formu-

las show how to calculate each of these losses. These

formulas assume continuous mode operation, so they

should not be used for calculating efficiency at light load

currents.

Switch loss:

ns I

SW OUT

OUT

() ( )

()( )( )

Boost current loss:

BOOST

OUT

()

0 008

Quiescent current loss:

OUT

()+ ()+







()

0 001

0 005

0 002

RSW = Switch resistance (≈ 0.4)

16ns = Equivalent switch current/voltage overlap time

f = Switch frequency

Example: with VIN = 10V, VOUT = 5V and IOUT = 1A:

BOOST

= ()( ) ( ) + 



 ()( )









= ()

()

()+ ()+() ( ) =

−

04 1

16 10

1 10 500 10

02 008

0 28

0 008 1 75

0 053

10 0 001

5 0 005

0 002

004

••

Total power dissipation is 0.28 + 0.053 + 0.04 = 0.37W.

Thermal resistance for LT1376 package is influenced by

the presence of internal or backside planes. With a full

plane under the SO package, thermal resistance will be

about 120

°C/W. No plane will increase resistance to about

160

°C/W. To calculate die temperature, use the proper

thermal resistance number for the desired package and

add in worst-case ambient temperature:

TJ = TA + θJA (PTOT)

With the SO-8 package (

θJA = 120°C/W), at an ambient

temperature of 70

°C,

TJ = 70 + 120 (0.37) = 114.4°C

Die temperature is highest at low input voltage, so use

lowest continuous input operating voltage for thermal

calculations.

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