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LT1375CS8 Datasheet(PDF) 21 Page - Linear Technology |
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LT1375CS8 Datasheet(HTML) 21 Page - Linear Technology |
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21 / 28 page ![]() 21 LT1375/LT1376 APPLICATIONS INFORMATION 77dB at low frequency, rolling off to unity-gain at 20kHz. Phase shows a two-pole characteristic until the ESR of the output capacitor brings it back above 10kHz. Phase mar- gin is about 60 ° at unity-gain. Analog experts will note that around 1kHz, phase dips very close to the zero phase margin line. This is typical of switch- ing regulators, especially those that operate over a wide range of loads. This region of low phase is not a problem as long as it does not occur near unity-gain. In practice, the variability of output capacitor ESR tends to dominate all other effects with respect to loop response. Variations in ESR will cause unity-gain to move around, but at the same time phase moves with it so that adequate phase margin is maintained over a very wide range of ESR ( ≥ ±3:1). What About a Resistor in the Compensation Network? It is common practice in switching regulator design to add a “zero” to the error amplifier compensation to increase loop phase margin. This zero is created in the external network in the form of a resistor (RC) in series with the compensation capacitor. Increasing the size of this resis- tor generally creates better and better loop stability, but there are two limitations on its value. First, the combina- tion of output capacitor ESR and a large value for RC may cause loop gain to stop rolling off altogether, creating a gain margin problem. An approximate formula for RC where gain margin falls to zero is: R Loop V G G ESR C OUT MP MA Gain = 1 ()=()( )( )( ) 242 . GMP = Transconductance of power stage = 2A/V GMA = Error amplifier transconductance = 2 × 10–3 ESR = Output capacitor ESR 2.42 = Reference voltage With VOUT = 5V and ESR = 0.1Ω, a value of 5.17k for RC would yield zero gain margin, so this represents an upper limit. There is a second limitation however which has nothing to do with theoretical small signal dynamics. This resistor sets high frequency gain of the error amplifier, including the gain at the switching frequency. If switching frequency gain is high enough, output ripple voltage will appear at the VC pin with enough amplitude to muck up proper operation of the regulator. In the marginal case, subharmonic switching occurs, as evidenced by alternat- ing pulse widths seen at the switch node. In more severe cases, the regulator squeals or hisses audibly even though the output voltage is still roughly correct. None of this will show on a theoretical Bode plot because Bode is an amplitude insensitive analysis. Tests have shown that if ripple voltage on the VC is held to less than 100mVP-P, the LT1376 will be well behaved. The formula below will give an estimate of VC ripple voltage when RC is added to the loop, assuming that RC is large compared to the reactance of CC at 500kHz. V R G V V ESR VL f C RIPPLE C MA IN OUT IN ( ) = ()( ) − ()( )( ) ()( )( ) 24 . GMA = Error amplifier transconductance (2000µMho) If a computer simulation of the LT1376 showed that a series compensation resistor of 3k gave best overall loop response, with adequate gain margin, the resulting VC pin ripple voltage with VIN = 10V, VOUT = 5V, ESR = 0.1Ω, L = 10 µH, would be: V k V C RIPPLE ( ) − − = () − ()( )( ) () = 3 2 10 10 5 0 1 2 4 10 10 10 500 10 0 144 3 63 •. . •• . This ripple voltage is high enough to possibly create subharmonic switching. In most situations a compromise value (< 2k in this case) for the resistor gives acceptable phase margin and no subharmonic problems. In other cases, the resistor may have to be larger to get acceptable phase response, and some means must be used to control ripple voltage at the VC pin. The suggested way to do this is to add a capacitor (CF) in parallel with the RC/CC network on the VC pin. Pole frequency for this capacitor is typically set at one-fifth of switching frequency so that it provides significant attenuation of switching ripple, but does not add unacceptable phase shift at loop unity-gain frequency. With RC = 3k, C fR k pF F C = ()( )( )= () = 5 2 5 2 500 10 3 531 3 π π • |
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