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AN4635 Datasheet(PDF) 23 Page - STMicroelectronics |
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AN4635 Datasheet(HTML) 23 Page - STMicroelectronics |
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23 / 34 page ![]() DocID027290 Rev 1 23/34 AN4635 Power consumption comparison 33 Figure 8. Three different settings of peripheral clock divider The power trace of the DMA operated example is different from the interrupt or blocking mode code execution. There is a peak in half of the transmission, caused by the half message interrupt. Then for half of the reply data reception the core stays in Sleep mode, it is only active during the second half. Different arrangement is of course possible. Table 10. Configurations - Clock divider Curve in Figure 8 Black Purple Green Idle mode between transmissions Stop JTAG interface OFF Current average over phases 2, 3 and 4 9.42 µA 9.16 µA 9.08 µA Clock 250 kHz MSI Voltage regulator Range 3 AHB/APB ratio 1/1 1/4 1/8 ULP/FWU +/+ Baud rate 9600 SW used DMA operation (Com DMA) |
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