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other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.

FEATURES 

DIRECT REPLACEMENT FOR INTERSIL LS3N165 

ABSOLUTE MAXIMUM RATINGS

Maximum Temperatures 

Storage Temperature ‐65°C to +200°C 

Operating Junction Temperature ‐55°C to +150°C 

Lead Temperature (Soldering, 10 sec.) 

+300°C 

Maximum Power Dissipation 

Continuous Power Dissipation (one side) 

300mW 

Total Derating above 25°C

4.2 mW/°C 

MAXIMUM CURRENT

Drain Current 

50mA 

MAXIMUM VOLTAGES 

Drain to Gate or Drain to Source

Peak Gate to Source

3

±125V 

Gate‐Gate Voltage 

±80V 

LS3N165 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)

SYMBOL 

CHARACTERISTIC 

MIN 

TYP. 

MAX 

UNITS 

CONDITIONS 

Gate Reverse Leakage Current 

‐‐ 

‐‐ 

10  

 

pA 

Gate Forward Current  

‐‐ 

‐‐ 

‐10 

 

‐‐ 

‐‐ 

‐25 

Drain to Source Leakage Current 

‐‐ 

‐‐ 

‐200 

Source to Drain Leakage Current 

‐‐ 

‐‐ 

‐400 

Drain Current “On” ‐5.0 

‐‐ 

‐30 

mA 

Gate to Source Threshold Voltage ‐2.0 

‐‐ 

‐5.0 

V 

‐2.0 

‐‐ 

‐5.0 

VDS =  VGS ,   ID = ‐10µA 

Drain to Source “On” Resistance 

‐‐ 

‐‐ 

300 Ω 

VGS = ‐20V,   ID = ‐100µA 

Forward Transconductance 

1500 

‐‐ 

3000 

µS 

VDS = ‐15V,    ID = ‐10mA ,   f = 1kHz 

Output Admittance 

‐‐ 

‐‐ 

300 

‐‐ 

‐‐ 

3  

pF 

 

VDS = ‐15V,    ID = ‐10mA ,   f = 1MHz

Reverse Transfer Capacitance 

‐‐ 

‐‐ 

0.7 

Output Capacitance 

‐‐ 

‐‐ 

3.0 

Common Source Forward 

Transconductance 

1200 

‐‐ 

‐‐ 

µS 

MATCHING CHARACTERISTICS LS3N165                                                                                                                                      

SYMBOL 

CHARACTERISTIC 

LIMITS  

UNITS 

 

CONDITIONS 

MIN 

MAX 

Forward Transconductance Ratio 

0.90 

1.0 

ns 

Gate Source Threshold Voltage 

Differential 

‐‐ 

100 

mV 

Gate Source Threshold Voltage 

Differential Change with Temperature 

‐‐ 

100 

µV/°C 

 

 

  

                                  SWITCHING TEST CIRCUIT 

The LS3N165 is a monolithic dual enhancement mode P-Channel Mosfet

LS3N165

P-CHANNEL MOSFET

Note 1 ‐ Absolute maximum ratings are limiting values above which LS3N165 serviceability may be impaired. 

* 

Note 2 – Per Transistor 

Note 3 – Device must not be tested at ±125V more than once or longer than 300ms. 

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The LS3N165 is a dual enhancement mode P-Channel

Mosfet and is ideal for space constrained applications

and those requiring tight electrical matching.

The hermetically sealed TO-78 package is well suited

for high reliability and harsh environment applications.

(See Packaging Information).

Tel: +44 1603 788967

Device Schematic

TO-78 (Bottom View)

Available Packages:

LS3N165 in TO-72

LS3N165 in bare die.

Please contact Micross for full

package and die dimensions

LS3N165 Features:

Very high Input Impedance

Low Capacitance

High Gain

High Gate Breakdown Voltage

Low Threshold Voltage

SWITCHING WAVEFORM & TEST CIRCUIT

*To avoid possible damage to the device while wiring, testing, or in actual 

operation, follow these procedures: To avoid the build‐up of static charge, the 

leads of the devices should remain shorted together with a metal ring except 

when being tested or used. Avoid unnecessary handling. Pick up devices by the 

case instead of the leads. Do not insert or remove devices from circuits with the 

power on, as transient voltages may cause permanant damage to the devices.