PIC18F2680ISPQTP datasheet(91/482 Pages) MICROCHIP

91 / 482 page

Preliminary

DS39625C-page 89

PIC18F2585/2680/4585/4680

5.4.3.1

FSR Registers and the

INDF Operand

At the core of indirect addressing are three sets of

registers: FSR0, FSR1 and FSR2. Each represents a

pair of 8-bit registers, FSRnH and FSRnL. The four

upper bits of the FSRnH register are not used, so each

FSR pair holds a 12-bit value. This represents a value

that can address the entire range of the data memory

in a linear fashion. The FSR register pairs, then, serve

as pointers to data memory locations.

Indirect addressing is accomplished with a set of

Indirect File Operands, INDF0 through INDF2. These

can be thought of as “virtual” registers: they are

mapped in the SFR space, but are not physically

implemented. Reading or writing to a particular INDF

the data at the address indicated by FSR1H:FSR1L.

Instructions that use the INDF registers as operands

actually use the contents of their corresponding FSR as

a pointer to the instruction’s target. The INDF operand

is just a convenient way of using the pointer.

Because indirect addressing uses a full 12-bit address,

data RAM banking is not necessary. Thus, the current

contents of the BSR and the Access RAM bit have no

effect on determining the target address.

FIGURE 5-7:

INDIRECT ADDRESSING

FSR1H:FSR1L

Data Memory

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

Bank 3

through

Bank 13

ADDWF, INDF1, 1

Using an instruction with one of the

indirect addressing registers as the

operand....

...uses the 12-bit address stored in

the FSR pair associated with that

...to determine the data memory

location to be used in that operation.

In this case, the FSR1 pair contains

ECCh. This means the contents of

location ECCh will be added to that

of the W register and stored back in

ECCh.

x x x x 1 1 1 0

1100 1 1 00

Bank 14

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