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AM29F040B Datasheet(PDF) 8 Page - Advanced Micro Devices |
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AM29F040B Datasheet(HTML) 8 Page - Advanced Micro Devices |
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8 / 30 page  8 Am29F040B P R E L I M I NARY Table 3. Am29F040B Autoselect Codes (High Voltage Method) Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously pro- tected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure re- quires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 19957. Contact an AMD representative to obtain a copy of the appropriate document. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Defi- nitions table). In addition, the following hardware data protection measures prevent accidental erasure or pro- gramming, which might otherwise be caused by spuri- ous system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent uninten- tional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the im- proper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em- bedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array Description A18–A16 A15–A10 A9 A8–A7 A6 A5–A2 A1 A0 Identifier Code on DQ7-DQ0 Manufacturer ID: AMD X X VID XVIL XVIL VIL 01h Device ID: Am29F040B X X VID XVIL XVIL VIH A4h Sector Protection Verification Sector Address XVID XVIL XVIH VIL 01h (protected) 00h (unprotected) |
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