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PIC18F2680ISPQTP Datasheet(PDF) 62 Page - Microchip Technology |
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PIC18F2680ISPQTP Datasheet(HTML) 62 Page - Microchip Technology |
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62 / 482 page  PIC18F2585/2680/4585/4680 DS39625C-page 60 Preliminary © 2007 Microchip Technology Inc. RXF12SIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDL(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu RXF11SIDL(6) 2585 2680 4585 4680 xxx- x-xx uuu- u-uu uuu- u-uu RXF11SIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu RXF10EIDL(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF10EIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF10SIDL(6) 2585 2680 4585 4680 xxx- x-xx uuu- u-uu -uuu uuuu RXF10SIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF9EIDL(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF9EIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF9SIDL(6) 2585 2680 4585 4680 xxx- x-xx uuu- u-uu -uuu uuuu RXF9SIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF8EIDL(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF8EIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF8SIDL(6) 2585 2680 4585 4680 xxx- x-xx uuu- u-uu -uuu uuuu RXF8SIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF7EIDL(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF7EIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF7SIDL(6) 2585 2680 4585 4680 xxx- x-xx uuu- u-uu -uuu uuuu RXF7SIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF6EIDL(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF6EIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu RXF6SIDL(6) 2585 2680 4585 4680 xxx- x-xx uuu- u-uu -uuu uuuu RXF6SIDH(6) 2585 2680 4585 4680 xxxx xxxx uuuu uuuu -uuu uuuu TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. |
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